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- [41] Lower bound estimation on the numbers of LUT blocks and micro-registers for time-multiplexed FPGA synthesis ERSA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS, 2003, : 321 - 324
- [42] FPGA-IMPLEMENTATION OF TIME-MULTIPLEXED MULTIPLE CONSTANT MULTIPLICATION BASED ON CARRY-SAVE ARITHMETIC FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 609 - +
- [43] ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 1800 - +
- [45] An Architecture and Timing-Driven Routing Algorithm for Area-Efficient FPGAs with Time-Multiplexed Interconnects 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 614 - 617
- [49] Towards the Least Complex Time-Multiplexed Constant Multiplication 2013 IFIP/IEEE 21ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2013, : 328 - 331
- [50] A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os 2006 IEEE International Conference on Field Programmable Technology, Proceedings, 2006, : 361 - 364