Advanced CMOS technology beyond 45nm node

被引：0

作者：

Kawanaka, Shigeru ^{[1
]}

Hokazono, Akira ^{[1
]}

Yasutake, Nobuaki ^{[1
]}

Tatsumura, Kosuke ^{[2
]}

Koyama, Masato ^{[2
]}

Toyoshima, Yoshiaki ^{[1
]}

机构：

[1] Semicond Co, Ctr Semicond Res & Dev, Isogo Ku, 8 Shinsugita Cho, Yokohama, Kanagawa 2358522, Japan

[2] Toshiba Co Ltd, Corp Res & Dev Ctr, Adv Lsi Technol Lab, Yokohama, Kanagawa 235, Japan

来源：

2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

At the time of CMOS device development in 45nm node, newly developed materials and techniques have been discussed and experimented to achieve power-performance requirement. Based on the published reports, the overview of current 45nm node technology development status is summarized. Then, the prevision of 32nm node device design strategy is discussed considering key technologies such as stress enhancement technique, metal high-k gate stack and non-classical device scaling both for structure and temperature.

引用

页码：164 / +

页数：2

共 50 条

[1] Technology modeling and characterization beyond the 45nm node
Nassif, Sani R.
2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 132 - 132
[2] Litho metrology challenges for the 45nm technology node and beyond
Allgair, John A.
Bunday, Benjamin D.
Bishop, Mike
Lipscomb, Pete
Orji, Ndubuisi G.
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XX, PTS 1 AND 2, 2006, 6152
[3] Double-Gate CMOS evaluation for 45nm technology node
Chiang, MH
An, JX
Krivokapic, Z
Yu, B
NANOTECH 2003, VOL 2, 2003, : 326 - 329
[4] Ion Implantation Technology and System for beyond 45nm node Devices
Tanjyo, Masayasu
Nagayama, Tsutomu
Hamamoto, Nariaki
Umisedo, Sei
Koga, Yuji
Maehara, Noriaki
Une, Hideyasu
Nogami, Takashi
Hino, Masayoshi
Kobayashi, Tomoaki
Fujita, Hideki
Matsumoto, Takao
Yoshimura, Yosuke
Sakai, Shigeki
Nagai, Nobuo
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1284 - 1287
[5] Ni-based FUSI gates: CMOS Integration for 45nm node and beyond
Hoffmann, T.
Veloso, A.
Lauwers, A.
Yu, H.
Tigelaar, H.
Van Dal, M.
Chiarella, T.
Kerner, C.
Kauerauf, T.
Shickova, A.
Mitsuhashi, R.
Satoru, I.
Niwa, M.
Rothschild, A.
Froment, B.
Ramos, J.
Nackaerts, A.
Rosmeulen, M.
Brus, S.
Vrancken, C.
Absil, P. P.
Jurczak, M.
Biesemans, S.
Kittl, J. A.
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 9 - +
[6] Design and CAD challenges in 45nm CMOS and beyond
Frank, David J.
Puri, Ruchir
Toma, Dorel
IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, : 497 - +
[7] Metal gate technology for 45nm and beyond
Shibahara, Kentaro
2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 105 - 106
[8] Air gap integration for the 45nm node and beyond
Daamen, R
Verheijden, GJAM
Bancken, PHL
Vandeweyer, T
Michelon, J
Hoang, VN
Hoofman, RJOM
Gallagher, MK
PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 240 - 242
[9] FOREMOST project will integrate 45nm CMOS technology
不详
ELECTRONICS WORLD, 2007, 113 (1852): : 6 - 6
[10] A novel current reference in 45nm cmos technology
Nagulapalli, R.
Hayatleh, K.
Barker, S.
Zourob, S.
Venkatareddy, A.
PROCEEDINGS OF THE 2017 IEEE SECOND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES (ICECCT), 2017,

← 1 2 3 4 5 →