MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory

被引:14
作者
Amirany, Abdolah [1 ]
Moaiyeri, Mohammad Hossein [1 ]
Jafari, Kian [1 ]
机构
[1] Shahid Beheshti Univ, Fac Elect Engn, Tehran, Iran
来源
2021 IEEE 51ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2021) | 2021年
关键词
Quaternary logic; Spintronic; Low power design; GAA-CNTFET; MTJ; CARBON NANOTUBE FETS; VIRTUAL-SOURCE MODEL; PERFORMANCE; CIRCUITS; DESIGN;
D O I
10.1109/ISMVL51352.2021.00037
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Multi-value logic (MVL) is one of the options considered by researchers to overcome the limitations of the conventional binary logic because of their remarkable features such as lower transmission power consumption, lower area, interconnect, and pins. Quaternary logic is one of the forms of MVLs that has received special attention due to its compatibility with binary logic. In this paper, a quaternary non-volatile memory cell is designed and simulated using the threshold voltage tunability feature of gate-all-around carbon nanotube field-effect transistor transistors (GAA-CNTFET) and non-volatile property of the magnetic tunnel junctions (MTJ). The simulation results show that while our proposed quaternary memory occupies a smaller area than the existing non-volatile quaternary memory, it consumes 31% and 33% lower average and static power, respectively. The Monte-Carlo simulations also show the correct operation of the proposed memory even in the presence of process variations.
引用
收藏
页码:172 / 177
页数:6
相关论文
共 32 条
  • [21] Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance
    Moaiyeri, Mohammad Hossein
    Razi, Farzad
    [J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2017, 16 (02) : 240 - 252
  • [22] Design and Evaluation of CNFET-Based Quaternary Circuits
    Moaiyeri, Mohammad Hossein
    Navi, Keivan
    Hashemipour, Omid
    [J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2012, 31 (05) : 1631 - 1652
  • [23] Nonvolatile Low-Cost Approximate Spintronic Full Adders for Computing in Memory Architectures
    Rajaei, Ramin
    Amirany, Abdolah
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 2020, 56 (04)
  • [24] Reliable, High-Performance, and Nonvolatile Hybrid SRAM/MRAM-Based Structures for Reconfigurable Nanoscale Logic Devices
    Rajaei, Ramin
    Amirany, Abdolah
    [J]. JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2018, 13 (09) : 1271 - 1283
  • [25] A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic
    Razi, Farzad
    Moaiyeri, Mohammad Hossein
    Rajaei, Ramin
    Mohammadi, Siamak
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2019, 18 : 598 - 605
  • [26] DPL-based novel CMOS 1-Trit Ternary Full-Adder
    Saha, Aloke
    Singh, Rakesh Kumar
    Gupta, Pragya
    Pal, Dipankar
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2021, 108 (02) : 218 - 236
  • [27] Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
    Shulaker, Max M.
    Hills, Gage
    Park, Rebecca S.
    Howe, Roger T.
    Saraswat, Krishna
    Wong, H. -S. Philip
    Mitra, Subhasish
    [J]. NATURE, 2017, 547 (7661) : 74 - +
  • [28] CONDUCTANCE AND EXCHANGE COUPLING OF 2 FERROMAGNETS SEPARATED BY A TUNNELING BARRIER
    SLONCZEWSKI, JC
    [J]. PHYSICAL REVIEW B, 1989, 39 (10): : 6995 - 7002
  • [29] A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation
    Wang, Chengzhi
    Zhang, Deming
    Zeng, Lang
    Deng, Erya
    Chen, Jie
    Zhao, Weisheng
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (04) : 1454 - 1464
  • [30] Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses
    Wang, Y.
    Zhang, Y.
    Deng, E. Y.
    Klein, J. O.
    Naviner, L. A. B.
    Zhao, W. S.
    [J]. MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 1774 - 1778