A Low Error Add and Shift-based Efficient Implementation of Base-2 Logarithm

被引:0
作者
Kareem, Pervaiz [1 ]
Naqvi, Syed Rameez [2 ]
Kyung, Chong-Min [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Sch Elect Engn, 291 Daehak Ro, Daejeon, South Korea
[2] COMSATS Inst Sci & Technol, Dept Elect Engn, GT Rd, Wah Cantt, Pakistan
来源
2017 INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING (ICEE) | 2017年
关键词
ELEMENTARY-FUNCTIONS; ALGORITHM;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A real-time and area-efficient hardware implementation of base-2 logarithm (log(2)) finds many applications. In this paper, we analyze previous shift and add-based approximations of logarithm. Based on the analysis we present a new two region add and shift-based method to approximate log(2) in hardware. The proposed approach results in 81.55% less percentage error and 42.85% less average error compared to previously reported best two region based approximation approaches with comparable area cost and latency. The proposed method uses most significant four bits of fractional part of shift and add-based method with different weights to approximate fractional part of log(2). Weights to these bits are assigned by simple addition, logical OR and logical AND operation to make hardware implementation more efficient.
引用
收藏
页数:6
相关论文
共 16 条
  • [1] CMOS VLSI implementation of a low-power logarithmic converter
    Abed, KH
    Siferd, RE
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2003, 52 (11) : 1421 - 1433
  • [2] Error analysis of the Kmetz/Maenner algorithm
    Arnold, M
    Bailey, T
    Cowles, J
    [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2003, 33 (1-2): : 37 - 53
  • [3] Low Cost Hardware Implementation of Logarithm Approximation
    Gutierrez, R.
    Valls, J.
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (12) : 2326 - 2330
  • [4] Implementation of elementary functions for logarithmic number systems
    Johansson, K.
    Gustafsson, O.
    Wanhammar, L.
    [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2008, 2 (04) : 295 - 304
  • [5] Juang T. -B., 2011, IEEE INT S VLSI DES, P1
  • [6] A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications
    Juang, Tso-Bing
    Chen, Sheng-Hung
    Cheng, Huang-Jia
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (12) : 931 - 935
  • [7] AN ALGORITHM FOR THE COMPUTATION OF BINARY LOGARITHMS
    KOSTOPOULOS, DK
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1991, 40 (11) : 1267 - 1270
  • [8] A FAST INTEGER BINARY LOGARITHM OF LARGE ARGUMENTS
    MAENNER, R
    [J]. IEEE MICRO, 1987, 7 (06) : 41 - 45
  • [9] Mitchell J. N., 1962, IRE Trans. Electron. Comput, VEC-11, P512, DOI [DOI 10.1109/TEC.1962.5219391, 10.1109/TEC.1962.5219391]
  • [10] A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
    Paul, Suganth
    Jayakumar, Nikhil
    Khatri, Sunil P.
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (02) : 269 - 277