DfT for the reuse of networks-on-chip as test access mechanism

被引：10

作者：

Amory, Alexandre M. ^{[1
]}

Ferlini, Frederico ^{[2
]}

Lubaszewski, Marcelo ^{[1
]}

Moraes, Fernando ^{[2
]}

机构：

[1] Univ Fed Rio Grande Sul Fed Univ, Inst Informat, Av Bento Goncalves,9500, Porto Alegre, RS, Brazil

[2] PUCRS Catholic Univ, Fac Informat, Porto Alegre, RS, Brazil

来源：

25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/VTS.2007.26

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents new DfT modules required to use networks-on-chip as test access mechanism. We demonstrate that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. network's without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. We analyse the DfT modules in terms of silicon area and test time, considering different network and test configurations.

引用

页码：435 / +

页数：2

共 18 条

[1]

Amory AM, 2006, PROC EUR TEST SYMP, P213

[2]

[Anonymous], ACM COMPUTING SURVEY

[3] Networks on chips: A new SoC paradigm [J].

Benini, L ;

De Micheli, G .

COMPUTER, 2002, 35 (01) :70-+

[4] Reusing an on-chip network for the test of core-based systems [J].

Cota, É ;

Carro, L ;

Lubaszewski, M .

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2004, 9 (04) :471-499

[5] The impact of NoC reuse on the testing of core-based systems [J].

Cota, E ;

Kreutz, M ;

Zeferino, CA ;

Carro, L ;

Lubaszewski, M ;

Susin, A .

21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, :128-133

[6]

Cota T, 2003, INT TEST CONF P, P612

[7]

Duato J., 2003, INTERCONNECTION NETW

[8] SOC test architecture design for efficient utilization of test bandwidth [J].

Goel, SK ;

Marinissen, EJ .

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2003, 8 (04) :399-429

[9] Design of reconfigurable access wrappers for embedded core based SoC test [J].

Koranne, S .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (05) :955-960

[10]

LI M, 2006, P ISVLSI

← 1 2 →