A 144Kb Annealing System Composed of 9x16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems

被引：42

作者：

Takemoto, Takashi ^{[1
]}

Yamamoto, Kasho ^{[2
]}

Yoshimura, Chihiro ^{[2
]}

Hayashi, Masato ^{[2
]}

Tada, Masafumi ^{[3
]}

Saito, Hiroaki ^{[4
]}

Mashimo, Mayumi ^{[2
]}

Yamaoka, Masanao ^{[2
]}

机构：

[1] Hitachi, Sapporo, Hokkaido, Japan

[2] Hitachi, Tokyo, Japan

[3] Toppan Tech Design Ctr, Sapporo, Hokkaido, Japan

[4] Total Design Serv, Sapporo, Hokkaido, Japan

来源：

2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) | 2021年 / 64卷

关键词：

D O I：

10.1109/ISSCC42613.2021.9365748

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：64 / +

页数：3

共 4 条

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[J]. NATURE, 2011, 473 (7346) : 194 - 198
[2] Su YQ, 2020, ISSCC DIG TECH PAP I, P480, DOI 10.1109/ISSCC19947.2020.9062938
[3] Takemoto T, 2019, ISSCC DIG TECH PAP I, V62, P52, DOI 10.1109/ISSCC.2019.8662517
[4] Yamamoto K, 2020, ISSCC DIG TECH PAP I, P138, DOI 10.1109/ISSCC19947.2020.9062965