Optimum supply and threshold voltages and transistor sizing effects on low power SOI circuit design

被引：0

作者：

Emadi, M. ^{[1
]}

Jafargholi, A. ^{[1
]}

Mogbadam, H. Sargazi ^{[2
]}

Nayebi, M. M. ^{[2
]}

机构：

[1] Sharif Univ Technol, Dept Elect Engn, VLSI Lab, Tehran, Iran

[2] Sharif Univ Technol, Dept Elect Engn, Tehran, Iran

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

low power design; energy-delay product; EDP contour; transistor sizing;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of V-dd=0-1-1.5V and V-th=0-0.8V, are analyzed to find optimal V-dd and V-th. BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and the formulations for finding the optimum gate sizing are also presented. Theses algorithms can be implemented in a CAD tool too.

引用

页码：1394 / +

页数：2

共 19 条

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