Flux trapping in superconducting circuits

It is widely accepted that flux trapping is one of the most serious problems that could create an integration limit for superconductor integrated circuits. The ultimate goal of our project is to reduce the problem to a set of routine technical recommendations for SFQ circuit design. To achieve the goal, we review known theories and recommendations for the reduction of flux trapping. Another important part of the project is an experimental verification of our suggestions. In this paper, we describe our experimental technique, which allows measurements to be carried out in real environments, for example, in a closed-cycle refrigerator or transport Dewar. To illustrate the advantages of our technique we discuss in detail the measured flux trapping properties of one test circuit: a 16-bit shift register. We found that the flux trapping properties of apparently similar cells vary dramatically from cell to cell. In other words, the effects of microscopic fabrication imperfections could be as important as layout optimization.