Design techniques for CMOS very-low-voltage operational amplifiers with enhanced power supply rejection ratio

被引：0
|
作者：
Lee, TS [1 ]
Liu, WC [1 ]
Chung, CT [1 ]
机构：
[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Yunlin 640, Taiwan
来源：
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Two very-low-voltage operational amplifiers in standard 0.35 mum CMOS process are presented. Simulation results are provided and the corresponding performances are discussed and compared. Simulation results indicate that those circuits show superior power supply rejection at high frequencies.
引用
收藏
页码：149 / 152
页数：4
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