Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme

被引：6

作者：

Chen, Wei-Chen ^{[1
]}

Lue, Hang-Ting ^{[1
]}

Hsieh, Chih-Chang ^{[1
]}

Wang, Keh-Chung ^{[1
]}

Lu, Chih-Yuan ^{[1
]}

机构：

[1] Macronix Int Co Ltd, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 01期

关键词：

Computer architecture; Microprocessors; Flash memories; Erbium; Hot carrier effects; Logic gates; Bit error rate; 3-D NAND; disturbance; dummy wordline (DWL); flash; hot carrier; pair bitline (BL); polycrystalline silicon; thin film transistor; two-step waveform;

D O I：

10.1109/TED.2019.2951460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we report two performance enhancement schemes for single-gate vertical-channel (SGVC) 3-D NAND Flash. The first one features a programming (PGM) waveform where the bias of the dummy wordline (DWL) is raised in a two-step manner so that the resultant disturbance that the DWL and edge WL suffer is appreciably alleviated. The second scheme takes advantage of a unique behavior termed "self-boosting-enhanced-PGM" mechanism in the pair- bitline PGM method to deal with the slow PGM bits and achieve a much lower bit error rate as a consequence. By using these two approaches, the bit error rate after multilevel cell (MLC) operation can be substantially improved by 82.

引用

页码：99 / 104

页数：6

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