A fabrication method for high performance embedded DRAM of 0.18um generation and beyond.

被引：0

作者：

Yoshida, T ^{[1
]}

Takato, H ^{[1
]}

Sakurai, T ^{[1
]}

Kokubun, K ^{[1
]}

Hiyama, K ^{[1
]}

Nomachi, A ^{[1
]}

Takasu, Y ^{[1
]}

Kishida, M ^{[1
]}

Ohtsuka, H ^{[1
]}

Naruse, H ^{[1
]}

Morimasa, Y ^{[1
]}

Yanagiya, N ^{[1
]}

Hashimoto, T ^{[1
]}

Noguchi, T ^{[1
]}

Miyamae, T ^{[1
]}

Iwabuchi, N ^{[1
]}

Tanaka, M ^{[1
]}

Kumagai, J ^{[1
]}

Ishiuchi, H ^{[1
]}

机构：

[1] Toshiba Corp, ULSI Device Engn Lab, Isogo Ku, Yokohama, Kanagawa 2350032, Japan

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852618

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new fabrication method for embedded DRAM of 0.18um generation is proposed, which realizes full compatibility of LOGIC process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block(SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics respecting both retention time and MOSFET AC/DC performance, promising high performance of SOC(System On a Chip) applications.

引用

页码：61 / 64

页数：4