Fabrication of field emitter arrays using the mold method for FED application

被引:5
作者
Cho, KJ
Ryu, JT
Lee, SY
机构
[1] Taegu Univ, Ctr Lab Facil, Kyungpook 712714, South Korea
[2] Taegu Univ, Dept Comp & Commun Engn, Kyungpook 712714, South Korea
[3] Kyungpook Natl Univ, Dept Phys, Taegu 702701, South Korea
关键词
mold; field emitter array; BPSG; anodic bonding; LPCVD;
D O I
10.1016/S0038-1101(02)00315-5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The typical mold method for FED fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by low pressure chemical vapor deposition (LPCVD), and then boro phospher silicate glass (BPSG) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed. (C) 2002 Published by Elsevier Science Ltd.
引用
收藏
页码:633 / 637
页数:5
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