Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

被引：42
作者：
Keshavarzi, A [1 ]
Roy, K [1 ]
Sachdev, M [1 ]
Hawkins, CF [1 ]
Soumyanath, K [1 ]
De, V [1 ]
机构：
[1] Intel Corp, Microprocessor Res Labs, Santa Clara, CA 95051 USA
来源：
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS | 2000年
关键词：
D O I：
10.1109/TEST.2000.894318
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Technology scaling challenges the effectiveness of current-based test techniques such as I-DDQ. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I-DDQ versus F-MAX (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I-DDQ versus temperature test can be deployed. Our data show that temperature (cooling from 110 degreesC to room) improved sensitivity of I-DDQ versus F-MAX two-parameter test by more than an order of magnitude (13.8X). The sensitivity can also be tuned by proper selection of a temperature range to match a required DPM level.
引用
收藏
页码：1051 / 1059
页数：9
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