A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

被引:6
作者
Haghbayan, Mohammad-Hashem [1 ]
Rahmani, Amir-Mohammad [1 ,2 ]
Miele, Antonio [3 ]
Fattah, Mohammad [1 ]
Plosila, Juha [1 ]
Liljeberg, Pasi [1 ]
Tenhunen, Hannu [1 ,2 ]
机构
[1] Univ Turku, Dept Informat Technol, Embedded Comp & Elect Syst Lab, FIN-20520 Turku, Finland
[2] Royal Inst Technol KTH, Dept Ind & Med Elect, S-16440 Kista, Sweden
[3] Politecn Milan, Dipartimento Elettron Informaz & Bioingn, I-20133 Milan, Italy
关键词
Online testing; functional testing; dark silicon; power capping; many-core systems; aging; lifetime reliability; OPTIMIZATION; SYSTEMS;
D O I
10.1109/TC.2015.2481411
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.
引用
收藏
页码:730 / 743
页数:14
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