A New Fault-Tolerant Multilevel Inverter Topology with Enhanced Reliability for PV Application

被引:6
作者
Kumar, Dhananjay [1 ]
Nema, Rajesh Kumar [1 ]
Gupta, Sushma [1 ]
Nema, Savita [1 ]
Dewangan, Niraj Kumar [2 ]
机构
[1] Maulana Azad Natl Inst Technol, Dept Elect Engn, Bhopal 462003, India
[2] Natl Inst Technol, Dept Elect Engn, Raipur 492010, Madhya Pradesh, India
关键词
Multilevel inverter; Fault-tolerant; Redundant leg; Reliability; Self-voltage balancing; POINT-CLAMPED CONVERTER; DESIGN; NUMBER;
D O I
10.1007/s13369-022-06992-2
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
Multilevel inverters (MLIs) have recently received a lot of attention in the power conditioning of photovoltaic (PV) applications. For a photovoltaic system, one of the indispensable necessities is reliability. This becomes even more vital in distant and isolated areas inaccessible for maintenance. The reliability of multilevel inverters used in photovoltaic systems is very low or vulnerable due to the high failure rate of power devices. Therefore, a new single-phase 9-level fault-tolerant topology multilevel inverter is proposed in this paper. The proposed 9-level fault-tolerant topology is able to tolerate single switch and multiple switch failures. Verification of fault-tolerance and source utilization is carried out from the experimental results and reliability evaluation is done mathematically. The process employs the analysis of failure rates of the switches and diodes of the multilevel inverter circuitry and estimation of reliability and mean time to failure (MTTF) is carried out before and after the employment of the proposed scheme using the Markov process. The sinusoidal pulse width modulation (SPWM) control method has been used as a modulation strategy to control the output voltage. The experimental results validate the effectiveness of the proposed 9-level fault-tolerant MLI topology during healthy, faulty and post-fault conditions is presented. In addition, the total harmonic distortion (THD) of the proposed 9-level fault-tolerant MLI topology during healthy and post-fault conditions is presented in the paper. Finally, the proposed 9-level fault-tolerant topology is a lesser device count compared with the existing topologies.
引用
收藏
页码:14841 / 14858
页数:18
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