CLOCK DUPLICITY FOR HIGH-PRECISION TIMESTAMPING IN GIGABIT ETHERNET

被引：0

作者：

Nicolau, Carles ^{[1
]}

Sala, Dolors ^{[1
]}

Canto, Enrique ^{[2
]}

机构：

[1] Univ Pompeu Fabra, Dept Informat & Commun Technol, Barcelona, Spain

[2] Univ Rovira & Virgili, Dept Elect Elect & Automat, Tarragona, Spain

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

TIME;

D O I：

10.1109/FPL.2009.5272258

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual mu P-based implementations fail on deterministic timestamp retrieval and insertion inside the message. This problem degrades significantly the synchronization between network nodes. This paper describes the analysis, implementation, and evaluation of a HW-timestamping technique for minimal-latency timestamping at Gigabit Ethernet using a low-cost off-the-shelf FPGA board. The effectiveness of the method is validated through a point-to-point synchronization scheme achieving a best-case synchronization accuracy of 150 ns.

引用

页码：379 / +

页数：2

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