A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

被引：3

作者：

Yin, Yong-Sheng ^{[1
]}

Liu, Liu ^{[1
]}

Chen, Hong-Mei ^{[1
]}

Deng, Hong-Hui ^{[1
]}

Meng, Xu ^{[1
]}

Wu, Jing-Sheng ^{[1
]}

Wang, Zhong-Feng ^{[2
]}

机构：

[1] Hefei Univ Technol, Inst VLSI Design, Hefei, Anhui, Peoples R China

[2] Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2019年 / 16卷 / 19期

基金：

中国国家自然科学基金;

关键词：

time-interleaved ADC; timing mismatch; channel multiplexing; wide bandwidth; BACKGROUND CALIBRATION; CONVERTER;

D O I：

10.1587/elex.16.20190540

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an all-digital calibration technique for time-interleaved ADC (TIADC) timing mismatch. The calibration architecture is based on a channel multiplexing architecture. For a M-channel TIADC, only one centralized calibration module is needed. Timing mismatches between channels are estimated by correlating the adjacent channel's outputs and a compensation algorithm based on the one-order five-point differentiator is employed to suppress the mismatches. Compared with conventional parallel calibration architecture, the proposed calibration architecture works well in higher Nyquist bands (NB) with high-scalability. The hardware consumption does not increase linearly with the number of sub-ADCs.

引用

页数：6

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