A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

被引：3

作者：

Yin, Yong-Sheng ^{[1
]}

Liu, Liu ^{[1
]}

Chen, Hong-Mei ^{[1
]}

Deng, Hong-Hui ^{[1
]}

Meng, Xu ^{[1
]}

Wu, Jing-Sheng ^{[1
]}

Wang, Zhong-Feng ^{[2
]}

机构：

[1] Hefei Univ Technol, Inst VLSI Design, Hefei, Anhui, Peoples R China

[2] Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2019年 / 16卷 / 19期

基金：

中国国家自然科学基金;

关键词：

time-interleaved ADC; timing mismatch; channel multiplexing; wide bandwidth; BACKGROUND CALIBRATION; CONVERTER;

D O I：

10.1587/elex.16.20190540

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an all-digital calibration technique for time-interleaved ADC (TIADC) timing mismatch. The calibration architecture is based on a channel multiplexing architecture. For a M-channel TIADC, only one centralized calibration module is needed. Timing mismatches between channels are estimated by correlating the adjacent channel's outputs and a compensation algorithm based on the one-order five-point differentiator is employed to suppress the mismatches. Compared with conventional parallel calibration architecture, the proposed calibration architecture works well in higher Nyquist bands (NB) with high-scalability. The hardware consumption does not increase linearly with the number of sub-ADCs.

引用

页数：6

共 50 条

[31] Recent Progress on Calibration Methods of Timing Skew in Time-Interleaved ADCS
Yang, Huijing
Zhang, Ruidong
Ren, Mingyuan
[J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2023, 32 (14)
[32] Channel Mismatch Background Calibration for Pipelined Time Interleaved ADCs
Mrassy, Armia
Dessouky, Mohamed
[J]. 2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012, : 609 - 612
[33] A simple, digital method for background estimation of timing mismatches in time-interleaved ADCs
Konopacki, Jacek
Machniewski, Jan
[J]. PRZEGLAD ELEKTROTECHNICZNY, 2022, 98 (09): : 174 - 177
[34] Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC
Asgar Abbaszadeh
Esmaeil N. Aghdam
Alfredo Rosado-Muñoz
[J]. Analog Integrated Circuits and Signal Processing, 2019, 99 : 299 - 310
[35] All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters
Chen, Shuai
Wang, Luke
Zhang, Hong
Murugesu, Rosanah
Dunwell, Dustin
Carusone, Anthony Chan
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (09) : 2552 - 2560
[36] Error detection and calibration for Time-Interleaved ADCs
Ping, Yifan
Yang, Xinquan
Kuang, Yin
Lin, Wei
[J]. 2014 XXXITH URSI GENERAL ASSEMBLY AND SCIENTIFIC SYMPOSIUM (URSI GASS), 2014,
[37] A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs
Tao, Yunsong
Zhong, Yi
Shao, Jin
Men, Changyou
Jie, Lu
Sun, Nan
[J]. 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
[38] A background calibration technique for multibit/stage pipelined and time-interleaved ADCs
El-Sankary, Kamal
Sawan, Mohamad
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (06) : 448 - 452
[39] Consecutive adaptive blind estimation of timing offsets for arbitrary channel time-interleaved ADCs
Shahmansoori, Arash
[J]. SIGNAL IMAGE AND VIDEO PROCESSING, 2015, 9 (01) : 45 - 55
[40] On the Compensation of Timing Mismatch in Two-Channel Time-Interleaved ADCs: Strategies and a Novel Parallel Compensation Structure
Wang, Yinan
Johansson, Hakan
Deng, Mingxin
Li, Zhiwei
[J]. IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2022, 70 : 2460 - 2475

← 1 2 3 4 5 →