An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

被引：1

作者：

Chen, Qingyu ^{[1
,2
]}

Wang, Haibin ^{[3
,5
]}

Chen, Li ^{[2
]}

Li, Lixiang ^{[6
]}

Zhao, Xing ^{[2
]}

Liu, Rui ^{[4
]}

Chen, Mo ^{[4
]}

Li, Xuantian ^{[4
]}

机构：

[1] Xian Microelect Technol Inst, Xian, Shaanxi, Peoples R China

[2] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada

[3] Univ Saskatchewan, Saskatoon, SK, Canada

[4] Univ Saskatchewan, Elect Engn, Saskatoon, SK, Canada

[5] Hohai Univ, Coll IOT Engr, Nanjing, Jiangsu, Peoples R China

[6] Dalhousie Univ, Halifax, NS, Canada

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2016年 / 32卷 / 03期

基金：

中国国家自然科学基金; 加拿大自然科学与工程研究理事会;

关键词：

SRAM; 12 T bitcell; Single event upset; Radiation hardening by design; CHARGE COLLECTION; DESIGN; UPSET; RELIABILITY; MITIGATION; MEMORIES; LAYOUT; CELL;

D O I：

10.1007/s10836-016-5586-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an SEU-resilient 12 T SRAM bitcell. Simulation results demonstrate that it has higher critical charge than the traditional 6 T cell. Alpha and proton testing results validate that it has a lower soft error rate compared to the reference designs for all data patterns and supply voltage levels. The improvement in SEU tolerance is achieved at the expense of 2X area penalty.

引用

页码：385 / 391

页数：7

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