CFET Design Options, Challenges, and Opportunities for 3D Integration

被引：17

作者：

Liebmann, L. ^{[1
]}

Smith, J. ^{[1
]}

Chanemougame, D. ^{[1
]}

Gutwin, P. ^{[1
]}

机构：

[1] America LLC, TEL Technol Ctr, Albany, NY 12203 USA

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720577

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Design details of standard cell architectures using complementary field effect transistors (CFET) are explored. The primary structural elements of CFET are reviewed and the layout impact of several 2nd-order technology constructs is analyzed. A manufacturability assessment and cost analysis of the resulting CFET technology-architecture definition is presented. Finally, the extendibility of CFET to 3.5-track cell height as well as higher-order 3D integration is explored.

引用

页数：4