Non-poisoning dual Damascene patterning scheme for low-k and ultra low-k BEOL

被引：0

作者：

Cote, W. ^{[1
]}

Edelstein, D. ^{[1
]}

Bunke, C. ^{[1
]}

Biolsi, P. ^{[1
]}

Wille, W. ^{[1
]}

Baks, H. ^{[1
]}

Conti, R. ^{[1
]}

Dalton, T. ^{[1
]}

Houghton, T. ^{[1
]}

Li, W-K. ^{[1
]}

Lin, Y-H. ^{[1
]}

Moskowitz, S. ^{[1
]}

Restaino, D. ^{[1
]}

Van Kleeck, T. ^{[1
]}

Vogt, S. ^{[1
]}

Ivers, T. ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Devel Ctr, Hopewell Jct, NY 12533 USA

来源：

ADVANCED METALLIZATION CONFERENCE 2006 (AMC 2006) | 2007年

关键词：

D O I：

暂无

中图分类号：

TF [冶金工业];

学科分类号：

0806 ;

摘要：

引用

页码：289 / 294

页数：6

共 7 条

[1] Angyal M, 2006, Advanced Metallization Conference 2005 (AMC 2005), P39
[2] Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
Edelstein, D
Davis, C
Clevenger, L
Yoon, M
Cowley, A
Nogami, T
Rathore, H
Agarwala, B
Arai, S
Carbone, A
Chanda, K
Cohen, S
Cote, W
Cullinan, M
Dalton, T
Das, S
Davis, P
Demarest, J
Dunn, D
Dziobkowski, C
Filippi, R
Fitzsimmons, J
Flaitz, P
Gates, S
Gill, J
Grill, A
Hawken, D
Ida, K
Klaus, D
Klymko, N
Lane, M
Lane, S
Lee, J
Landers, W
Li, WK
Lin, YH
Liniger, E
Liu, XH
Madan, A
Malhotra, S
Martin, J
Molis, S
Muzzy, C
Nguyen, D
Nguyen, S
Ono, M
Parks, C
Questad, D
Restaino, D
Sakamoto, A
[J]. PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 214 - 216
[3] Comprehensive reliability evaluation of a 90 mn CMOS technology with Cu/PECVD low-K BEOL
Edelstein, D
Rathore, H
Davis, C
Clevenger, L
Cowley, A
Nogami, T
Agarwala, B
Arai, S
Carbone, A
Chanda, K
Chen, F
Cohen, S
Cote, W
Cullinan, M
Dalton, T
Das, S
Davis, P
Demarest, J
Dunn, D
Dziobkowski, C
Filippi, R
Fitzsimmons, J
Flaitz, P
Gates, S
Gill, J
Grill, A
Hawken, D
Ida, K
Klaus, D
Klymko, N
Lane, M
Lane, S
Lee, J
Landers, W
Li, WK
Lin, YH
Liniger, E
Liu, XH
Madan, A
Malhotra, S
Martin, J
Molis, S
Muzzy, C
Nguyen, D
Nguyen, S
Ono, M
Parks, C
Questad, D
Restaino, D
Sakamoto, A
[J]. 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 316 - 319
[4] Full copper wiring in a sub-0.25 μm CMOS ULSI technology
Edelstein, D
Heidenreich, J
Goldblatt, R
Cote, W
Uzoh, C
Lustig, N
Roper, P
McDevitt, T
Motsiff, W
Simon, A
Dukovic, J
Wachnik, R
Rathore, H
Schulz, R
Su, L
Luce, S
Slattery, J
[J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 773 - 776
[5] KAANTA CW, 1991, P 8 INT IEEE VLSI MU, P144
[6] SANKARAN S, 2006, IN PRESS IEEE IEDM
[7] WILLE WC, 2006, Patent No. 7030031

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