Analysis of jitter in phase-locked loops

被引：56

作者：

Lee, DC ^{[1
]}

机构：

[1] Mentor Graph Corp, Allentown, PA 18103 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2002年 / 49卷 / 11期

关键词：

1/f noise; frequency dividers; jitter; oscillators; phase noise; phase-locked loops (PLLs); white noise;

D O I：

10.1109/TCSII.2002.807265

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Jitter in clock signals is analyzed, linking noise in free-running oscillators to short-term and long-term time-domain behavior of phase-locked loops. Particular attention is given to comparing the impact of 1/f noise and white noise in oscillators and frequency dividers on jitter in phase-locked loops of first-and second-order. Theoretical analysis is supported by results obtained using mixed-signal behavior simulation.

引用

页码：704 / 711

页数：8

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