Temperature effects of Si interface passivation layer deposition on high-k III-V metal-oxide-semiconductor characteristics

被引：12
|
作者：
Ok, InJo [1 ]
Kim, H. [1 ]
Zhang, M. [1 ]
Zhu, F. [1 ]
Park, S. [1 ]
Yum, J. [1 ]
Zhao, H. [1 ]
Lee, Jack C. [1 ]
机构：
[1] Univ Texas, Microelect Res Ctr, Dept Elect & Comp Engn, Austin, TX 78758 USA
来源：
APPLIED PHYSICS LETTERS | 2007年 / 91卷 / 13期
关键词：
D O I：
10.1063/1.2790780
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
In this work, we studied the electrical characteristics of TaN/HfO2/GaAs metal-oxide-semiconductor capacitors with Si interface passivation layer (IPL) under various postdeposition anneal (PDA) conditions and various Si deposition temperatures/times. Using optimal Si IPL under reasonable PDA, post metal anneal conditions, and various Si deposition temperatures, excellent electrical characteristics with low frequency dispersion (< 5%, and 50 mV) and reasonable D-it value (similar to 10(12) eV(-1) cm(-2)) can be obtained. It was found that higher temperature of Si IPL deposition and longer PDA time at 600 degrees C improved equivalent oxide thickness and leakage current. (c) 2007 American Institute of Physics.
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