2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

被引:38
作者
Thijssen, Bart J. [1 ,2 ]
Klumperink, Eric A. M. [1 ]
Quinlan, Philip [3 ]
Nauta, Bram [1 ]
机构
[1] Univ Twente, MESA Inst, Integrated Circuit Design Grp, NL-7500 AE Enschede, Netherlands
[2] Imec Netherlands, NL-5656 AE Eindhoven, Netherlands
[3] Analog Devices Inc, Integrated Networking Prod, Cork T12 X36X, Ireland
关键词
Receivers; Power demand; Inductors; Transconductance; Frequency conversion; Noise measurement; Baseband; Analog finite impulse response (FIR) filter; frequency divider; high selectivity; Internet of Things (IoT); low power; low-noise transconductance amplifier (LNTA); receiver; CMOS;
D O I
10.1109/JSSC.2020.3031493
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm(2). It consumes 370 mu W from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is >= 63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.
引用
收藏
页码:2007 / 2017
页数:11
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