Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

被引：24

作者：

Liu, Weihsing ^{[1
]}

Liu, Shen-Iuan ^{[2
,3
]}

机构：

[1] Natl Formosa Univ, Dept Elect Engn, Huwei 63201, Yun Lin County, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

[3] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2010年 / 63卷 / 02期

关键词：

Low voltage; Low-power; Multiplier; Weak inversion;

D O I：

10.1007/s10470-009-9382-y

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications. © Springer Science+Business Media, LLC 2009.

引用

页码：307 / 312

页数：6

共 28 条

[1] A 1.2V CMOS multiplier for 10 Gbit/s equalization [J].