ShareStreams: A scalable architecture and hardware support for high-speed QoS packet schedulers

被引：4

作者：

Krishnamurthy, R ^{[1
]}

Yalamanchili, S ^{[1
]}

Schwan, K ^{[1
]}

West, R ^{[1
]}

机构：

[1] IBM Res Corp, Zurich Labs, Zurich, Switzerland

来源：

12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FCCM.2004.52

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a unified hardware architecture for realizing a range of wire-speed packet scheduling disciplines for output link scheduling. This paper presents opportunities to exploit parallelism, design issues, tradeoffis and evaluation of the FPGA hardware architecture for use in switch network interfaces. The architecture uses processor resources for queueing & data movement and FPGA hardware resources for accelerating decisions and priorsity updates. The hardware architecture stores state in Register base blocks, stream service attributes are compared using single-cycle decision blocks arranged in a novel single-stage recirculating network. The architecture provides effective mechanisms to trade hardware complexity for lower execution-time in a predictable manner The hardware realized in a Virtex-I and Virtex-II FPGA can meet the packet-time requirements of 10Gbps links for 256 stream queues with window-constrained scheduling disciplines. The hardware can schedule 1536 stream queues with priority-class/fair-queueing scheduling disciplines using 16 service-classes to meet 10Gbps packet-times.

引用

页码：115 / 124

页数：10

共 13 条

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