Adiabatic circuits for low power logic

被引：0
作者：
Akers, LA [1 ]
Suram, R [1 ]
机构：
[1] Univ Missouri, Dept Elect & Comp Engn, Columbia, MO 65211 USA
来源：
2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Adiabatic logic circuits offer significant reductions in power dissipation when compared with standard static CMOS design. However, many implementation issues remain to be solved. This paper will discuss low power design and then focus on adiabatic logic circuits and the required power clock needed to drive them. A new power clock is presented which does not utilize any external components and provides the gradual rise, hold, and fall times required for adiabatic logic.
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页码：286 / 289
页数：4
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