Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

被引：29

作者：

Bohuslavskyi, H. ^{[1
]}

Barraud, S. ^{[1
]}

Barral, V. ^{[1
]}

Casse, M. ^{[1
]}

Le Guevel, L. ^{[1
]}

Hutin, L. ^{[1
]}

Bertrand, B. ^{[1
]}

Crippa, A. ^{[2
]}

Jehl, X. ^{[2
]}

Pillonnet, G. ^{[1
]}

Jansen, A. G. M. ^{[2
]}

Arnaud, F. ^{[3
]}

Galy, P. ^{[3
]}

Maurand, R. ^{[2
]}

De Franceschi, S. ^{[2
]}

Sanquer, M. ^{[2
]}

Vinet, M. ^{[1
]}

机构：

[1] CEA, LETI, Minatec Campus, F-38054 Grenoble, France

[2] Univ Grenoble Alpes, CEA, INAC, PHELIQS, F-38054 Grenoble, France

[3] STMicroelectronics, F-38920 Crolles, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2018年 / 65卷 / 09期

关键词：

28 nm fully depleted silicon-on-insulator (FD-SOI); body biasing; cryogenic electronics; quantum computing; ring oscillator (RO); ultralow power; QUANTUM COMPUTATION; CMOS; SILICON;

D O I：

10.1109/TED.2018.2859636

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Extensive electrical characterization of ring oscillators (ROs) made in high-kappa metal gate 28-nm fully depleted silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage (tau(P)), static current (I-STAT), and dynamic current (I-DYN) are analyzed for the case of the increase of threshold voltage (V-TH) observed at low temperature. Then, the same analysis is performed by compensating V-TH to a constant, temperature-independent value through forward body biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (V-DD) in order to find an optimal operating point combining both high RO frequencies and low-power dissipation. We show that the Energy-Delay product can be significantly reduced at low temperature by applying an FBB voltage (V-FBB). We demonstrate that outstanding performance of RO in terms of speed (tau(P) = 37 ps) and static current (7nA/stage) can be achieved at 4.3 K with V-DD reduced down to 0.325 V.

引用

页码：3682 / 3688

页数：7

共 26 条

[1]

[Anonymous], 2018, 2018 JT INT EUROSOI, DOI DOI 10.1109/ULIS.2018.8354742

[2]

Beigne E, 2015, PROC EUR S-STATE DEV, P164, DOI 10.1109/ESSDERC.2015.7324739

[3]

Bhushan M., 2015, CMOS METRICS MODEL E, P347

[4]

Bohuslavskyi H, 2017, IEEE SILICON NANOELE, P143, DOI 10.23919/SNW.2017.8242338

[5]

Charbon E, 2016, INT EL DEVICES MEET

[6] Design and Cryogenic Operation of a Hybrid Quantum-CMOS Circuit [J].

Clapera, P. ;

Ray, S. ;

Jehl, X. ;

Sanquer, M. ;

Valentian, A. ;

Barraud, S. .

PHYSICAL REVIEW APPLIED, 2015, 4 (04)

[7]

Gutierrez D. EA, 2001, Low Temp. Electron., P105, DOI [10.1016/B978-012310675-9/50003-7, DOI 10.1016/B978-012310675-9/50003-7]

[8] The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS [J].

Homulle, Harald ;

Song, Lin ;

Charbon, Edoardo ;

Sebastiano, Fabio .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01) :263-270

[9]

Homulle H, 2017, 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT), P25, DOI 10.1109/FPT.2017.8280117

[10]

Hutin L., 2016, 2016 IEEE S VLSI TEC, P1, DOI [10.1109/VLSIT.2016.7573380, DOI 10.1109/VLSIT.2016.7573380]

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