Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

被引:0
|
作者
Yi, Boram [1 ]
Yang, Geun Soo [2 ]
Barraud, Sylvain [3 ]
Bervard, Laurent [3 ]
Lee, Jae Woo [4 ]
Yang, Ji-Woon [4 ]
机构
[1] Samsung Co, Design Enablement Team, Hwaseong, South Korea
[2] Samsung Co, Semicond R&D Ctr, Hwaseong, South Korea
[3] Univ Grenoble Alpes, CEA LETI, Minatec Campus, Grenoble, France
[4] Korea Univ, Dept Elect & Informat Engn, Sejong, South Korea
关键词
Compact model; Gate-all-around MOSFETs; Low-frequency noise; Nanowire MOSFETs; 1/F NOISE;
D O I
10.1016/j.sse.2021.108223
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, the bias dependence of low-frequency noise (LFN) in nanowire type gate-all-around (GAA) MOSFETs was physically modeled. In the model, the inversion carrier density distribution was considered based on the potential in the channel that changes according to the bias. The developed model was verified with measurement data of the fabricated device. The model could help circuit designers to optimize noise performance in analog/RF applications when designing integrated circuits using nanowire-type GAA MOSFETs.
引用
收藏
页数:4
相关论文
共 50 条
  • [21] Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate
    Lee, JS
    Ha, DW
    Choi, YK
    King, TJ
    Bokor, J
    IEEE ELECTRON DEVICE LETTERS, 2003, 24 (01) : 31 - 33
  • [22] On the asymmetry of the DC and low-frequency noise characteristics of vertical nanowire MOSFETs with bulk source contact
    Simoen, Eddy
    Veloso, Anabela
    Matagne, Philippe
    SOLID-STATE ELECTRONICS, 2022, 191
  • [23] Trap and 1/f-noise effects at the surface and core of GaN nanowire gate-all-around FET structure
    Reddy, Mallem Siva Pratap
    Im, Ki-Sik
    Lee, Jung-Hee
    Caulmione, Raphael
    Cristoloveanu, Sorin
    NANO RESEARCH, 2019, 12 (04) : 809 - 814
  • [24] In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets
    Cretu, B.
    Veloso, A.
    Simoen, E.
    SOLID-STATE ELECTRONICS, 2023, 201
  • [25] 1/f Noise in 3D Vertical Gate-all-around Junction-less Silicon Nanowire Transistors
    Mukherjee, Chhandak
    Maneux, Cristell
    Pezard, Julien
    Larrieu, Guilhem
    2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, : 34 - 37
  • [26] Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model
    Najam, Faraz
    Yu, Yun Seop
    Cho, Keun Hwi
    Yeo, Kyoung Hwan
    Kim, Dong-Won
    Hwang, Jong Seung
    Kim, Sansig
    Hwang, Sung Woo
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (08) : 2457 - 2463
  • [27] Compact Drain Current Model of Silicon-Nanotube-based Double Gate-All-Around (DGAA) MOSFETs Incorporating Short Channel Effects
    Kumar, Arun
    Srinivas, P. S. T. N.
    Tiwari, Pramod Kumar
    2019 IEEE 14TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2019,
  • [28] Impact of Self-Heating on Linearity Performance of In0.53Ga0.47As-Based Gate-All-Around MOSFETs
    Srinivas, P. S. T. N.
    Tiwari, Pramod Kumar
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2022, 22 (01) : 42 - 49
  • [29] Defects and Low-Frequency Noise in Irradiated Black Phosphorus MOSFETs With HfO2 Gate Dielectrics
    Liang, C. D.
    Ma, R.
    Su, Y.
    O'Hara, A.
    Zhang, E. X.
    Alles, M. L.
    Wang, P.
    Zhao, S. E.
    Pantelides, S. T.
    Koester, S. J.
    Schrimpf, R. D.
    Fleetwood, D. M.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2018, 65 (06) : 1227 - 1238
  • [30] A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics
    Lime, Francois
    Moldovan, Oana
    Iniguez, Benjamin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (09) : 3036 - 3041