Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?

被引：0

作者：

Fummi, F ^{[1
]}

Marconcini, C ^{[1
]}

Pravadelli, G ^{[1
]}

机构：

[1] Univ Verona, Dipartimento Informat, I-37100 Verona, Italy

来源：

ETS 2004: NINTH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2004年

关键词：

functional verification; ATPG; fault model; fault coverage;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.

引用

页码：154 / 159

页数：6

共 14 条

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