Design techniques for 1.5-V low-power CMOS current-mode cyclic analog-to-digital converters

Design techniques to realize low-voltage low-power (LVLP) cyclic current-mode analog-to-digital converters (IADC's) in the CMOS digital process are presented. First, a modified reference-nonrestoring (MRN) algorithm is proposed. By using the MRN algorithm, the digital correction (DCN) technique can be embedded into the cyclic architecture to reduce the linearity errors caused by the comparator inaccuracy and the offset of the sample/hold (S/H) operations. Moreover, new LVLP fully differential current-mode circuits performing the S/H, multiplication-by-2, and current comparison are also developed to implement the cyclic IADC without the use of linear capacitors or a multithreshold process. An experimental chip for the proposed IADC with an active area of 4 mm(2) has been fabricated in 0.8 mu m n-well CMOS technology. With a 1.5-V supply voltage, the fabricated IADC achieves 10-bit resolution with the differential nonlinearity (DNL) of 0.63 LSB and integral nonlinearity (INL) of 1.4 LSB when operated at a 12-ks/s conversion rate. The power consumption of the IADC core circuit is 2 mW.