A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC

被引：73

作者：

Matin, M ^{[1
]}

Saha, A

Cooper, JA

机构：

[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA

[2] Purdue Univ, Birck Nanotechnol Ctr, W Lafayette, IN 47907 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2004年 / 51卷 / 10期

关键词：

counter-doping; DMOS; high-voltage MOSFET; nitric oxide (NO) anneal; self-aligned; short-channel; SiC;

D O I：

10.1109/TED.2004.835622

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to less than or equal to0.5 mum, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.

引用

页码：1721 / 1725

页数：5

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