A symbolic simulation-based ANSI/IEEE Std 1149.1 compliance checker and BSDL generator

被引：5

作者：

Singh, H ^{[1
]}

Patankar, G ^{[1
]}

Beausang, J ^{[1
]}

机构：

[1] Synopsys Inc, Mt View, CA 94043 USA

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

D O I：

10.1109/TEST.1997.639621

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper shows how to extract the boundary-scan circuitry from an IC (Integrated Circuit), verify its compliance to IEEE Std 1149.1 and generate its BSDL (Boundary Scan Description Language) description. This work applies to the 75% of boundary-scan ICs that have hand-generated or macro-cell based boundary-scan circuitry. It also applies to boundary-scan ICs designed using RTL (Register Transfer Level) synthesis.

引用

页码：256 / 264

页数：9