Parallel architectures for decision-directed RLS-equalization

被引:0
作者
Drewes, C [1 ]
Hammerschmidt, JS [1 ]
Hutter, AA [1 ]
机构
[1] Tech Univ Munich, Inst Integrated Circuits, Bridgelab, D-80290 Munich, Germany
来源
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Parallel architectures for decision-directed adaptive recursive least-squares (RLS) equalizers based on a QR-decomposition (QRD) using square-root free Givens-rotations are derived that allow very high throughput for broadband applications. We apply an algorithmic optimization that leads to the use of additional fast adder trees together with a re-timing of the required arithmetic components to maximize throughput. A hybrid RLS/least-mean-squares equalizer is further proposed allowing even higher throughput. The complexity of the resulting equalizer structures is compared for an eight-tap decision-feedback equalizer in terms of an equivalent NAND gate count.
引用
收藏
页码:93 / 96
页数:4
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