An FPGA-Based Implementation of Variable Fractional Delay Filter

被引：2

作者：

Nithirochananont, Ussanai ^{[1
]}

Chivapreecha, Sorawat ^{[1
]}

Dejhan, Kobchai ^{[1
]}

机构：

[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Dept Telecommun Engn, Bangkok 10520, Thailand

来源：

CSPA: 2009 5TH INTERNATIONAL COLLOQUIUM ON SIGNAL PROCESSING AND ITS APPLICATIONS, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/CSPA.2009.5069197

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization.

引用

页码：104 / 107

页数：4

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