Comparing reliability-redundancy tradeoffs for two von Neumann multiplexing architectures

Nanoelectronic systems are anticipated to be highly susceptible to computation and communication noise. Interestingly, von Neumann addressed the issue of computation in the presence, of noisy gates in 1952 and developed a technique called multiplexing. He proposed multiplexing architectures based on two universal logic functions, NAND and MAJ. Generalized combinatorial models to analyze such multiplexing architectures were proposed by von Neumann and extended later by others. In this work, we describe an automated method for computing the effects of noise in both the computational and interconnect hardware of multiplexing-based nanosystems-a method employing a probabilistic model checking tool and extending previous modeling efforts, which only considered gate noise. This method is compared with a recently proposed automation methodology based on probabilistic transfer matrices and used to compute and compare the reliability of individual NAND and MAJ multiplexing systems, both in the presence of gate and interconnect noise. Such a comparative study of NAND and MAJ multiplexing is needed to provide quantitative guidelines for choosing one of the multiplexing schemes. The maximum device failure probabilities that can be accommodated by multiplexing-based fault-tolerant nanosystems are also computed by this method and compared with theoretical results from the literature. This paper provides a framework that can capture probabilistically quantified fault models and provide quick reliability evaluation of multiplexing architectures.