A clustering engine for data rate reduction in the Belle II pixel detector

The DEPFET technology has been chosen as the baseline for the vertex pixel detector of the Belle II experiment at KEK\Japan. This detector consist of 22 modules, each proposed to be equipped with 2 x 250 x 512 pixel. With the proposed average readout frequency of 10kHz and 30kHz peak rate a huge data stream of approx. 100Gbit/s will be generated. To reduce this data stream to a more feasible value, we have to take advantage of the low occupancy of approx. 1-2% and the the hit distribution within the pixel array. For this purpose a pipelined clustering algorithm was developed, which can handle cluster sizes of 3 x 3 or 5 x 5 at full readout speed. These algorithm can handle data from non bricked sensors and also from bricked designs. It is able to reduce the data rate by up to 50%. The collection of the clustered data packages from the row wise parallel pipeline are controlled by a specially developed output scheduler, which assures together with the corresponding FIFO structures the data-handling capability. In this paper we will present the overall structure of such a DCE (Data Clustering Engine) and also the details of the implemented clustering and output scheduling algorithms. Furthermore the impacts of the constraints on speed, power and area on the developed circuit and the chosen realization given by the experiment environment will be discussed in detail.