DEMAC: A Modular Platform for HW-SW Co-Design

被引:0
作者
Perdomo, Diego A. Roa [1 ]
Kabrick, Ryan [1 ]
Diaz, Jose M. Monsalve [1 ,2 ]
Raskar, Siddhisanket [1 ,2 ]
Fox, Dawson [1 ]
Gao, Guang R. [1 ]
机构
[1] Univ Delaware, Newark, DE 19716 USA
[2] Argonne Natl Lab, Lemont, IL USA
来源
PROCEEDINGS OF FOURTH ANNUAL WORKSHOP ON EMERGING PARALLEL AND DISTRIBUTED RUNTIME SYSTEMS AND MIDDLEWARE (IPDRM 2020) | 2020年
基金
美国国家科学基金会;
关键词
Dataflow Model; Codelet Model; Program Execution Model; DARTS; Many-core architecture; Cluster; Software-Hardware Co-design; FPGA; Exa-scale;
D O I
10.1109/IPDRM51949.2020.00008
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Scientists running applications on high performance computers expect these systems to deliver a high throughput effectively and reliably, while maintaining flexibility, programmability and energy efficiency. Programs are usually translated from a coded language that defines the operation of these systems through a compiler. HPC machines exhibit different features and behaviors based on their architectural characteristics: they could have accelerators or be a collection of computational units with a non-uniform memory access. Aiming to develop a low-cost, flexible and versatile parallel machine for hardware-software co-design of program execution models research, we present DEMAC (the Delaware Modular Assembly Cluster). It provides the necessary tools to develop and test novel features for the next generation of supercomputers. It includes a set of 3D-printed frames that can house several card-sized multi-core embedded systems. Along with a full open source stack, these small computers feature Parallella boards containing a Zynq-7000 series SoC with a dual-core ARM processor and an FPGA that interconnects with a 16-core co-processor called Epiphany. All individual nodes are connected through an Ethernet network. An initial version of a runtime based on Dataflow's Codelet Model is also proposed. This project aims to provide a flexible research platform that could benefit different research labs looking for low-cost parallel platforms.
引用
收藏
页码:25 / 32
页数:8
相关论文
共 19 条
  • [1] Generating Fine-Grain Multithreaded Applications Using a Multigrain Approach
    Arteaga, Jaime
    Zuckerman, Stephane
    Gao, Guang R.
    [J]. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2017, 14 (04)
  • [2] A parallel program execution model supporting modular software construction
    Dennis, JB
    [J]. THIRD WORKING CONFERENCE ON MASSIVELY PARALLEL PROGRAMMING MODELS, PROCEEDINGS, 1998, : 50 - 60
  • [3] Gao GuangR., 2011, CAPSL TECHNICAL MEMO
  • [4] Geng T., 2020, PDAWL PROFILE BASED
  • [5] Geng T., 2016, LANGUAGES COMPILERS
  • [6] Compiling C for the EARTH multithreaded architecture
    Hendren, LJ
    Tang, XN
    Zhu, YC
    Gao, GR
    Xue, X
    Cai, HY
    Ouellet, P
    [J]. PROCEEDINGS OF THE 1996 CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT '96), 1996, : 12 - 23
  • [7] Hum H., 1995, P PAR ARCH COMP TECH
  • [8] Hurn HHJ, 1996, INT J PARALLEL PROG, V24, P319
  • [9] Joshua S., 2014, THESIS U DELAWARE NE
  • [10] Khan R. L., 2012, US Patent, Patent No. [WO2012067688A1, 2012067688]