Configurable parallel memory implementation for system-on-chip designs

被引：0

作者：

Vanne, J ^{[1
]}

Aho, E ^{[1
]}

Kuusilinna, K ^{[1
]}

Hämäläinen, T ^{[1
]}

机构：

[1] Tampere Univ Technol, Inst Digital & Comp Syst, FIN-33720 Tampere, Finland

来源：

SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS | 2003年

关键词：

configurable parallel memory architecture; permutation; DRAM controller; pipelining;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

System-on-chip (SoC) designs with parallel on-chip memories increase the memory bandwidth and feed the processor with only necessary data. This paper presents the implementation of a novel Configurable Parallel Memory Architecture (CPMA) that offers plenty of design and run-time configuration possibilities. CPMA is shown to decrease considerably the processor-memory bottleneck by widening the memory bandwidth, decreasing the number of memory accesses, and diminishing the significance of memory latency.

引用

页码：237 / 248

页数：12

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