A comparative analysis of dual edge triggered flip-flops

被引：0

作者：

Chung, WM ^{[1
]}

Sachdev, M ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

2000 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CONFERENCE PROCEEDINGS, VOLS 1 AND 2: NAVIGATING TO A NEW ERA | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A dual edge, triggered (DET) flip-flop responds to both edges of the clock. Hence the usage of DET flip-flops reduces clock related power dissipation in digital YLSIs. DET flip-flops are also desirable in high performance applications since clock frequency can be halved for the same data throughput. In this article; we compare several published implementations of DET flip-flops for performance, power consumption. A modified DET flip-flop is proposed that exhibits improved specifications. Preliminary simulations are also carried out to evaluate DET flip-flop sensitivities to VDD, temperature, clock and data rise times, etc.

引用

页码：564 / 568

页数：5

共 9 条

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