Track-and-Hold and Comparator for a 12.5GS/s, 8bit ADC

被引：3

作者：

Ghetmiri, Shohreh ^{[1
]}

Salama, C. Andre T. ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/MWSCAS.2009.5236083

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8bit, 12.5GS/s folding-interpolating analog to digital converter (ADC) with a 3GHz bandwidth. The circuits are implemented in a 0.25 mu m, 190GHz SiGe BiCMOS process. The THA occupies an area of 0.5mm(2). It features a SNDR of 47dB or 7.5bits ENOB for a 3GHz bandwidth, a hold time of 21ps with a droop rate of 11mV/80ps and a power dissipation of 230mW from a 3.3V supply. The comparator occupies an area of 0.38mm(2) and exhibits an input sensitivity of +/-2mV, an input offset voltage of 1.5mV, latch and recovery times of 19 and 21ps respectively and a power dissipation of 150mW from a 3.3V supply.

引用

页码：353 / 356

页数：4

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