An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

被引：19

作者：

Ok, Sunghwa ^{[1
]}

Chung, Kyunghoon ^{[1
]}

Koo, Jabeom ^{[1
]}

Kim, Chulwoo ^{[1
]}

机构：

[1] Korea Univ, Dept Elect Engn, Seoul 136713, South Korea

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2010年 / 18卷 / 07期

关键词：

Antiharmonic lock; delay-locked loop (DLL); false lock; frequency multiplication; limited locking range; DELAY-LOCKED LOOP; ADAPTIVE BANDWIDTH CONTROL; CLOCK GENERATOR; RANGE; SYNTHESIZER; OSCILLATOR; NOISE; CYCLE; PLL;

D O I：

10.1109/TVLSI.2009.2019757

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-mu m CMOS process, occupies an active area of 0.043 mm(2), and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.

引用

页码：1130 / 1134

页数：5

共 19 条

[1]

BEST RE, 1998, PHASE LOCKED LOOPS T

[2] A wide-range delay-locked loop with a fixed latency of one clock cycle [J].

Chang, HH ;

Lin, JW ;

Yang, CY ;

Liu, SI .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (08) :1021-1027

[3] A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications [J].

Chien, G ;

Gray, PR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) :1996-1999

[4]

CHUANG CN, 2007, IEEE INT SOLID STATE, P172

[5] A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction [J].

Du, Qingjin ;

Zhuang, Jingcheng ;

Kwasniewski, Tad .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (11) :1205-1209

[6] A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os [J].

Farjad-Rad, R ;

Nguyen, A ;

Tran, JM ;

Greer, T ;

Poulton, J ;

Dally, WJ ;

Edmondson, JH ;

Senthinathan, R ;

Rathi, R ;

Lee, MJE ;

Ng, HT .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (09) :1553-1561

[7] A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips [J].

Farjad-Rad, R ;

Dally, W ;

Ng, HT ;

Senthinathan, R ;

Lee, MJE ;

Rathi, R ;

Poulton, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (12) :1804-1812

[8] CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator [J].

Foley, DJ ;

Flynn, MP .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :417-423

[9] A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator [J].

Kim, C ;

Hwang, IC ;

Kang, SM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (11) :1414-1420

[10] A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling [J].

Kim, Jin-Han ;

Kwak, Young-Ho ;

Kim, Mooyoung ;

Kim, Soo-Won ;

Kim, Chulwoo .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (09) :2077-2082

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