Design and Performance Optimization of Dopingless Vertical Nanowire TFET Using Gate Stacking Technique

This paper focuses on the impact of gate stacking (SiO2+HfO2) on dopingless vertical nanowire TFET (designed with gate-on-source technique) with an equivalent oxide thickness (EOT) of 0.8 nm and SiO2 thickness of 0.5 nm. Here, the charge plasma technique is used for doping on an intrinsic silicon substrate by using platinum (with work function of 5.93 eV) on the source side metal and hafnium (with work function of 3.9 eV) as the gate 1 metal. The proposed gate-stacked charge plasma vertical nanowire tunnel FET (GS-CPVNWTFET) device is simulated in ATLAS-2D, and the performance metrics are investigated. The paper compares three different combinations of SiO2 and HfO2 (with SiO2 thicknesses of 0.3 nm, 0.4 nm and 0.5 nm) and then the analog and RF parameters, such as I-D-V-GS and I-D-V-DS characteristics, input transconductance (g(m)), transconductance to drive current ratio (g(m)/I-D), gate to source capacitance (C-GS), gate to drain capacitance (C-GD), total gate capacitance (C-GG), unity gain cut-off frequency (f(T)), output transconductance (g(d)), output resistance (r(O), early voltage (V-EA), intrinsic gain (A(V)) and gain bandwidth product (GBP), and the structural performance for all three combinations are obtained. The proposed GS-CPVNWTFET device exhibits I-ON of 19.182 mu A/mu m, I-OFF of 7.05 x 10(-17) A/mu m, ratio of ON current to OFF current (I-ON/I-OFF) - 2.72 x 10(11), subthreshold slope (SS) of 10.80 mV/decade and DIBL of 3.17 mV/V. Later, a comparison is carried out between conventional CPVNWTFET and gate-stacked CPVNWTFET, and it is observed that the proposed GS-CPVNWTFET device with gate-on-source technique shows better analog and structural performance.