A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer

被引：19

作者：

Kong, Long ^{[1
,2
]}

Razavi, Behzad ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Elect Engn Dept, Los Angeles, CA 90095 USA

[2] Oracle, Mixed Signal Design Grp, Santa Clara, CA 95054 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2017年 / 52卷 / 08期

关键词：

Sigma Delta noise; cascaded phase-locked loop (PLL); fractional-N synthesizer; noise filter; noise trap; PLL; DELTA-SIGMA MODULATOR; FREQUENCY-SYNTHESIZER; PLL; LOOP;

D O I：

10.1109/JSSC.2017.2686838

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the Sigma Delta modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated jitter of 1.68 ps(rms).

引用

页码：2117 / 2127

页数：11

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