An 8-bit, 200 MSPS folding and interpolating ADC

被引：0

作者：

Moldsvor, O ^{[1
]}

Ostrem, GS ^{[1
]}

机构：

[1] Nordic VLSI ASA, N-7075 Tiller, Norway

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 1998年 / 15卷 / 01期

关键词：

ADC; folding and interpolation; BiCMOS; high speed;

D O I：

10.1023/A:1008232613620

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8-bit, 200 MSPS folding and interpolating analog-to-digital converter, ADC, has been implemented in a 1.2 mu m BiCMOS-process. It achieves 7.5 effective bits with a power dissipation of 575mW. The active area is 4mm(2). The implementation and measured results are presented. A simple analytical model for the interpolation-induced nonlinearity in a folding and interpolating ADC using sinusoidal folding is presented. The bowing of the reference ladder due to interaction with the input stages is analyzed, and analytical models are derived.

引用

页码：37 / 47

页数：11

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