A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

被引:17
作者
Dohar, Suraj Singh [1 ]
Siddharth, R. K. [1 ]
Vasantha, M. H. [1 ]
Kumar, Nithin Y. B. [1 ]
机构
[1] Natl Inst Technol Goa, Dept Elect & Commun Engn, Ponda 403401, India
关键词
Low power circuits; reliability; single event upset (SEU); static noise margin (SNM); static random access memory (SRAM) cell; MEMORY CELL;
D O I
10.1109/TED.2021.3064899
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this article, a highly reliable radiationhardened-by-design (RHBD) 10T static random access memory (SRAM) cell is proposed. In space, the impact of alpha particles and cosmic radiation flips the node data resulting in loss of data in conventional 6T SRAM. The proposed SRAM has quad-nodes, which stores the data. The architecture is designedwith a quad-latch topology and simulated in 65-nm CMOS technology with a supply voltage of 1.2 V. The result shows that the design can tolerate both 0 to 1 and 1 to 0 single event upset errors on any one of its nodes. The read and write access times of the proposed design are 88.78 and 241.77 ps, respectively. The static noise margin for read, write, and hold operations are 379.01, 906.51, and 637.1 mV, respectively. The proposed architecture takes an area of 6.52 mu m(2).
引用
收藏
页码:2265 / 2270
页数:6
相关论文
共 16 条
  • [1] Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies
    Bota, Sebastia A.
    Torrens, Gabriel
    Verd, Jaume
    Segura, Jaume
    [J]. SOLID-STATE ELECTRONICS, 2015, 111 : 104 - 110
  • [2] Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    Calhoun, Benton H.
    Chandrakasan, Anantha P.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (07) : 1673 - 1679
  • [3] Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
    Guo, Jing
    Zhu, Lei
    Sun, Yu
    Cao, Huiliang
    Huang, Hai
    Wang, Tianqi
    Qi, Chunhua
    Zhang, Rongsheng
    Cao, Xuebing
    Xiao, Liyi
    Mao, Zhigang
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (05) : 991 - 994
  • [4] Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology
    Guo, Jing
    Xiao, Liyi
    Mao, Zhigang
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (07) : 1994 - 2001
  • [5] A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
    Jahinuzzaman, Shah M.
    Rennie, David J.
    Sachdev, Manoj
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) : 3768 - 3773
  • [6] Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications
    Jiang, Jianwei
    Xu, Yiran
    Zhu, Wenyi
    Xiao, Jun
    Zou, Shichang
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (03) : 967 - 977
  • [7] Jung IS, 2012, MIDWEST SYMP CIRCUIT, P714
  • [8] Lin S, 2011, 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), P320, DOI 10.1109/ICCD.2011.6081418
  • [9] A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate
    Nayak, Debasish
    Acharya, Debiprasad Priyabrata
    Rout, Prakash Kumar
    Nanda, Umakanta
    [J]. MICROELECTRONICS JOURNAL, 2018, 73 : 43 - 51
  • [10] Low-cost highly-robust hardened cells using blocking feedback transistors
    Nicolaidis, Michael
    Perez, Renaud
    Alexandrescu, Dan
    [J]. 26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2008, : 371 - +