A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

被引：20

作者：

Dohar, Suraj Singh ^{[1
]}

Siddharth, R. K. ^{[1
]}

Vasantha, M. H. ^{[1
]}

Kumar, Nithin Y. B. ^{[1
]}

机构：

[1] Natl Inst Technol Goa, Dept Elect & Commun Engn, Ponda 403401, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2021年 / 68卷 / 05期

关键词：

Low power circuits; reliability; single event upset (SEU); static noise margin (SNM); static random access memory (SRAM) cell; MEMORY CELL;

D O I：

10.1109/TED.2021.3064899

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, a highly reliable radiationhardened-by-design (RHBD) 10T static random access memory (SRAM) cell is proposed. In space, the impact of alpha particles and cosmic radiation flips the node data resulting in loss of data in conventional 6T SRAM. The proposed SRAM has quad-nodes, which stores the data. The architecture is designedwith a quad-latch topology and simulated in 65-nm CMOS technology with a supply voltage of 1.2 V. The result shows that the design can tolerate both 0 to 1 and 1 to 0 single event upset errors on any one of its nodes. The read and write access times of the proposed design are 88.78 and 241.77 ps, respectively. The static noise margin for read, write, and hold operations are 379.01, 906.51, and 637.1 mV, respectively. The proposed architecture takes an area of 6.52 mu m(2).

引用

页码：2265 / 2270

页数：6

共 16 条

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