Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB

被引：10

作者：

Smets, Quentin ^{[1
]}

Schram, Tom ^{[1
]}

Verreck, Devin ^{[1
]}

Cott, Daire ^{[1
]}

Groven, Benjamin ^{[1
]}

Ahmed, Zubair ^{[1
]}

Kaczer, Ben ^{[1
]}

Mitard, Jerome ^{[1
]}

Wu, Xiangyu ^{[1
]}

Kundu, Souvik ^{[1
]}

Mertens, Hans ^{[1
]}

Radisic, Dunja ^{[1
]}

Thiam, Arame ^{[1
]}

Li, Waikin ^{[1
]}

Dupuy, Emmanuel ^{[1
]}

Tao, Zheng ^{[1
]}

Vandersmissen, Kevin ^{[1
]}

Maurice, Thibaut ^{[1
]}

Lin, Dennis ^{[1
]}

Morin, Pierre ^{[1
]}

Asselberghs, Inge ^{[1
]}

Radu, Iuliana ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720517

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present an analysis of gate length scaling of WS2 transistors fully fabricated in a 300mm pilot line. Despite low channel mobility, I-max,100 mu A/mu m is enabled by low side contact resistance R-c=1.3 +/- 1.0k Omega-mu m at n=3 x 10(13) cm(-2). Hysteresis of 5mV/V at moderate electric fields is demonstrated. High single-device yield and low variability is achieved, and it is established that I-on correlates mainly with mobility and less with SS and V-t. We demonstrate that switch-off can still be achieved with extremely scaled L-g=2nm, but significant short-gate effects occur due to thick CET and unoptimized device configuration. We show better short-gate control with connected dual gate configuration. TCAD simulations identify the main performance bottlenecks and a path towards improved device performance over Silicon FETs.

引用

页数：4

共 2 条

[1] Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
Asselberghs, I
Smets, Q.
Schram, T.
Groven, B.
Verreck, D.
Afzalian, A.
Arutchelvan, G.
Gaur, A.
Cott, D.
Maurice, T.
Brems, S.
Kennes, K.
Phommahaxay, A.
Dupuy, E.
Radisic, D.
De Marneffe, J-F
Thiam, A.
Li, W.
Devriendt, K.
Huyghebaert, C.
Lin, D.
Caymax, M.
Morin, P.
Radu, I. P.
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
[2] Low-Temperature Physical Adsorption for the Nucleation of Sub-10 nm Al2O3 Gate Stack on Top-Gated WS2 Transistors
Lin, Yu-Shu
Hoo, Ju-Yu
Chung, Tsai-Fu
Yang, Jer-Ren
Chen, Miin-Jang
ACS APPLIED ELECTRONIC MATERIALS, 2020, 2 (05) : 1289 - 1294

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