A novel SEU hardened SRAM bit-cell design

被引：8

作者：

Li, Tiehu ^{[1
,2
]}

Yang, Yintang ^{[1
]}

Zhang, Junan ^{[2
]}

Liu, Jia ^{[2
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian 710071, Shaanxi, Peoples R China

[2] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 12期

关键词：

SRAM; single event upset; radiation hardening by design; CMOS TECHNOLOGY; ROBUST;

D O I：

10.1587/elex.14.20170413

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

引用

页数：8

共 50 条

[1] A novel highly reliable and low-power radiation hardened SRAM bit-cell design
Lin, Dianpeng
Xu, Yiran
Liu, Xiaonian
Zhu, Wenyi
Dai, Lihua
Zhang, Mengying
Li, Xiaoyun
Xie, Xin
Jiang, Jianwei
Zhu, Huilong
Zhang, Zhengxuan
Zou, Shichang
IEICE ELECTRONICS EXPRESS, 2018, 15 (03):
[2] OPTIMIZATION OF 8T SRAM BIT-CELL DESIGN
Wu, Luping
Wang, Chunhsiung
Mo, Hongxiang
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,
[3] A novel SEU tolerant SRAM data cell design
Zhang, Guohe
Zeng, Yunlin
Liang, Feng
Chen, Kebin
IEICE ELECTRONICS EXPRESS, 2015, 12 (17):
[4] CMOS latch bit-cell array for low-power SRAM design
Chung, Yeonbae
Cheng, Weijie
IEICE ELECTRONICS EXPRESS, 2010, 7 (15): : 1145 - 1151
[5] Bit-Cell Selection Analysis for embedded SRAM-based PUF
Alheyasat, A.
Torrens, G.
Bota, S.
Alorda, B.
2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
[6] Low power and high write speed SEU tolerant SRAM data cell design
Wang Li
Zhang GuoHe
Zeng YunLin
Shao ZhiBiao
SCIENCE CHINA-TECHNOLOGICAL SCIENCES, 2015, 58 (11) : 1983 - 1988
[7] Double-node-upset aware SRAM bit-cell for aerospace applications
Prasad, Govind
Mandi, Bipin Chandra
Ali, Maifuz
MICROELECTRONICS RELIABILITY, 2022, 133
[8] Read Disturb-Free SRAM Bit-Cell for Subthreshold Memory Applications
Kim, Hyunmyoung
Kim, Taehoon
Manisankar, Sivasundar
Chung, Yeonbae
2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2017,
[9] A Radiation Hardened SRAM Cell-DSRL
Wu, Shuxiao
Li, Lei
Ren, Lei
PROCEEDINGS OF 2016 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2016, : 274 - 278
[10] SEU Tolerant SRAM Cell
Sarkar, Sudipta
Adak, Anubhav
Singh, Virendra
Saluja, Kewal
Fujita, Masahiro
2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2011, : 597 - 602

← 1 2 3 4 5 →