COPPER ELECTROPLATING PROCESS FOR MSAP RESISTANT TO ETCH-INDUCED PITTING

The rollout of 5G technology is leading electronics circuity and IC substrate manufacturers to require higher densities in their designs. Due to the nature of 5G applications, high reliability and exceptional electrical performance in these designs are also increasingly important. To meet these needs, fabricators have gradually established the manufacturing capabilities to build boards using modified Semi-Additive Processing (mSAP). The copper plating electrolyte for mSAP needs to fill blind micro-vias, plate fine lines, and plate through holes simultaneously. One of the challenges in mSAP, however, are V-pits generated in the electroplated copper surface during the final flash etching step. Since these pitting defects might severely reduce the reliability in the final product, an additional baking step is currently used in the process flow to anneal the plated copper. This baking step takes several hours, increasing costs and decreasing throughput significantly. Therefore, innovative copper electroplating solutions that can provide via filling and fine line plating resolution capabilities and a copper deposit that can be etched uniformly across the surface during the flash etching step are desirable. The purpose of this study was to investigate the underlying pitting mechanism and to develop such a plating process to reduce pit formation. The factors that have effects on pitting formation, such as the type of plating electrolyte including additive package selection and optimization, etching rate and baking condition are discussed. The developed plating process, MacuSpec VF-TH 300, showed excellent via fill capability, great fine line resolution, and high throwing power for through hole plating in a single bath. The tensile strength and elongation of the deposit exceed the IPC class III requirements.