Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

被引：6

作者：

Ker, Ming-Dou ^{[1
]}

Wang, Chang-Tzu ^{[1
,2
]}

Tang, Tien-Hao ^{[2
]}

Su, Kuan-Cbeng ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 30039, Taiwan

[2] United Microelect Corp, Reliabil Technol & Assurance Div, ESD Engn Dept, Hsinchu, Taiwan

来源：

2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL | 2007年

关键词：

D O I：

10.1109/RELPHY.2007.369967

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1xVDD devices for 3xVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mu m CMOS process with only 1.2-V devices.

引用

页码：594 / +

页数：2

共 5 条

[1]

Anderson W. R., 1998, P EOS ESD S, P54

[2]

Ker M.-D., 2005, IEEE INT SOL STAT CI, P524

[3] Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations [J].

Ker, MD ;

Lin, KH .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (02) :235-246

[4] Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors [J].

Ker, Ming-Dou ;

Chen, Shih-Lun ;

Tsai, Chia-Sheng .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (09) :1934-1945

[5] Stacked PMOS clamps for high voltage power supply protection [J].

Maloney, TJ ;

Kan, W .

ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 1999, 1999, :70-77

← 1 →