Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation

The contemporary network-on-chips (NoCs) have highly complex architectures. So, robust post-silicon validation mechanism is required for error-proof NoC design. Traces of packet transactions are generated during NoC validation and are stored for fault analysis. Size of trace generated, directly translates into on-chip storage cost and communication bandwidth requirement. Our work proposes a modified NoC router architecture which eliminates the redundant traces and only stores the meaningful traces. This results in reduction of total trace amount while maintaining the same level of system internal observability. The scheme is proved to he henelicial for short-lived communication faults (packet drop, direction fault etc.), and shows around 23% to 36% of trace reduction in case of a 8x8 mesh network for each cycle trace capture. The overhead introduced is nominal and can further he reduced in case of permanent network faults.